Senior Architect DDR/HBM PHY

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a seasoned expert in high-speed interface principles with a deep understanding of mixed-signal design and off-chip signaling. You have a proven track record of generating and supporting comprehensive documentation through written specifications and possess exceptional communication skills to convey these specifications within a design team and to external customers. You are adept at RTL logic design, simulation, test planning, and verification of complex integrated circuit components. Your knowledge extends to design-for-test, timing analysis, power analysis, behavioral modeling, and synthesis constraints. With at least 12 years of relevant experience, you have honed your skills in troubleshooting and debugging mixed-signal interfaces. You thrive in a collaborative, multi-site team environment and are passionate about translating customer desires into innovative product design features and functions. Your expertise will be pivotal in driving the development of next-generation DDR and HBM PHYs in the Synopsys IP portfolio.

• Understanding marketing and customer desires for Synopsys' DDR and HBM PHY interface performance and functionality.
• Translating those desires into a set of product design features and functions.
• Generating the functional description for the product, creating specifications describing the interface components, operation, structure, and behavioral parameters.
• Optimizing the design for performance, power, and area.
• Interacting and communicating with design teams performing logical design, logical verification, analog circuit design and verification, and layout design.
• Supporting customers in their implementation of the product.
• Tracking industry developments through standards committees, representing Synopsys in these committees.

• Drive the innovation and development of high-performance DDR and HBM PHY interfaces.
• Ensure Synopsys' products meet and exceed market and customer expectations.
• Enhance the functionality and performance of Synopsys' IP portfolio through cutting-edge design and optimization.
• Strengthen Synopsys' presence and influence in standards committees and industry developments.
• Facilitate seamless integration and implementation of Synopsys products for customers worldwide.
• Contribute to the overall success and technological advancement of Synopsys.

• Deep understanding of high-speed interface principles, such as mixed-signal design and off-chip signaling.
• Expertise in generating and supporting documentation through written specifications.
• Proficiency in RTL logic design, simulation, test planning, and verification of complex integrated circuit components.
• Knowledge of design-for-test, timing analysis, power analysis, behavioral modeling, and synthesis constraints.
• Strong troubleshooting and debugging skills for mixed-signal interfaces.
• Minimum of 12 years of related experience.

You are a collaborative team player with excellent communication skills and the ability to work across multi-site teams. You are detail-oriented, highly analytical, and capable of addressing complex and multi-dimensional issues. Your extensive experience and mastery-level knowledge position you as a pre-eminent expert in your field. You are driven by innovation and have a strategic mindset that aligns with Synopsys' goals and objectives.

You will join a collaborative, multi-person engineering team engaged in similar activities on related DDR and HBM PHY development projects. This team is dedicated to planning and executing the design for the next-generation DDR and HBM PHYs in the Synopsys IP portfolio, ensuring that Synopsys remains at the forefront of technological innovation.