Sr. Process Engineer

The Process Engineering group at Skyworks in Woburn, Massachusetts is responsible for developing and supporting all wafer fabrication processes used to produce Skyworks' diverse portfolio of products. The primary device technologies include HBT, BiFET, pHEMT, BiHEMT and Silicon diodes at various performance nodes. The group works closely with the Advanced Technology Development team to develop technologies and with the Manufacturing Operations team to deliver world-class quality products to market.

• Support Advanced Technology Development projects by developing and thoroughly characterizing robust unit processes as building blocks of next-generation technologies.
• Once released to Production, take ownership of the unit processes in the Final Process section. This includes sustaining process performance and driving continuous capability improvement.
• Support daily production to ensure on-time-delivery of top quality product. This includes disposition of held lots and prescribing appropriate rework processing as necessary. May require leading a team to rapidly contain yield/quality excursions and drive corrective actions.
• Participate in fab-wide/section-specific continuous improvement efforts affecting key metrics.
• Engage in professional development opportunities to stay in tune with industry trends, extend the state of the art and enhance the group's technical and professional depth and breadth.
• Build teamwork and cohesiveness within the group, and champion collaboration between engineering groups to improve the wellbeing and performance of the overall organization.
• Work with Operations synergistically, following a "work cell" model, to optimize the overall performance of the Final Process area & enhance the skills/knowledge of Operations personnel.

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• At a minimum, a BS in engineering, physics, chemistry, material science or related discipline.
• At least 4 years of experience in micro-electronics process engineering with primary experience in final (i.e. backside) processes including wafer mount/dismount, thinning/grinding and dicing/singulation. An ideal candidate will also have some knowledge/experience in other process areas such as thin films, dry etch and/or wet processes. A basic understanding of HBT/HEMT device physics and common PCM test structures and test parameters are pluses.
• A working knowledge of common figures of merit (and the factors that control them) for final wafer processing such as flatness, thickness, roughness, flexural strength, critical dimensions, back-to-front alignment and metal sheet resistance. Also, experience applying analytical tools (e.g. SEM/FIB/EDX) and interpreting the results.
• Metrics-driven, data directed, detail oriented and very strong in core engineering principles.
• Team player with experience driving for improved process control and rapidly containing yield/quality excursions, identifying root causes and implementing effective corrective actions.
• An insatiable desire to understand cause and effect, and the mechanisms that connect them.
• Intermediate knowledge and practical experience applying structured problem solving methods (e.g. Shainin, Six Sigma or Model-based) to identify and control or eliminate root causes of variation.
• Intermediate knowledge and practical experience applying SPC, DOE, MSA and ANOVA.
• Intermediate data analysis skills using tools such as JMP, Exensio/Spotfire or dataPower.
• Ideally, a basic knowledge of Lean and the Theory of Constraints.
• Excellent verbal and written "360 degree" communication skills.
• Initiative to address and appropriately escalate problems to achieve rapid resolution.
• Ability to work effectively with engineering peer groups to influence change and drive improvements in a dynamic and collaborative environment that values lasting results.
• Ability and willingness to work in a cleanroom semiconductor processing environment.
• Ability to work with other engineering resources across various shifts.