Interconnect System Architect

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and deliveringtrustedexperience to customers and partnersworldwideand we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues togrowthe ability to deploy new offerings and hardware infrastructure on time, inhigh volume with high quality and lowest cost is of paramount importance. To achieve this goal, theCloud Hardware Systems Engineering (CHSE)team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery,scaleand sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions,insightand industry knowledge to envision and implement future technical solutions that will manage andoptimizethe Cloud infrastructure.

We are looking for anInterconnect SystemArchitectto join the System Design team.

TheInterconnect SystemArchitectdrivesco-design efforts between silicon and system teams, integratingcutting-edgeinterconnect technologies. This role is pivotal for next-generation high-speed connectivity solutions across Microsoft hardwareplatforms.The ideal candidate will havedemonstrated significant experienceinhigh speedsystem designwith advanced interconnectivity technologies.Our team is at the forefront of technology and system design, leading the way for the next generation of platforms. Our mission is to architect the most performant, secure, reliable, and cost-effective solutions that are deployed at hyperscale to power Azure. The architect filling this role will be the subject matter expertto address the interconnectivity challenge in the silicon package, in themodule, in the tray, in the rack and in the cluster.The architect will collaborate with the Planning and Sourcing teams and with Mechanical and Thermal Architects on requirements capture, technology insertion, concept proposals, cost/performance tradeoffs, prototype engineering, and architectural documentation for design/planning reviews. Once a program is approved from a conceptual level, the Architect willpartnerwith the development teams to ensure a smooth transition to full product development.

This individual willalsochampion innovative technical principles, design strategyand forward-looking technologies related to industry trends,drivethe codesign withthe fullhardwarestackfrom silicon tonode,rackand cluster.Helping articulate and define our nextgenerationinterconnectivity technology.

Come join this exciting and growing teamthroughour monumental evolution ofcloud hardware atAzure and Microsoft!

ThisInterconnect System Architectrole will require you todrive innovation, partnerships, anddevelopment:

• Lead silicon-system co design for high speed electrical and optical interconnects (die to die, package, board, cable/backplane), ensuring coherent requirements flow between SoC/ASIC, packaging, module, and system architectures.

• Drivethe interconnect technology roadmap,define inflection points, readiness criteria, and insertion plans across near , mid , and long term horizons; drive make/buy/partner decisions with clear TCO, risk, and schedule tradeoffs.

• Drive end to end SI/PI performance, spanningpackagemoduletrayrackclusterto deliver scalable bandwidth density, latency, power, and reliability targets. Work withSIteam toestablishchannel budgets;guide stack ups, materials, connector/cable selections; standardize modeling, simulation, and validation methodologies for BER/jitter, crosstalk, S parameters, and compliance.

• Represent Microsoft at industry conferences/consortia and in standards efforts (OIF, IEEE, OCP, OFC, etc.),publish/present to advance ecosystem alignment.

• Influence roadmaps with PHY, connector, substrate,PCB,cable, and optical vendors;evaluateemerging technologies; incubate POCs that de risk insertion into program plans.

Required Qualifications:

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:
• Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• BS/MS in Electrical Engineering, Computer Engineering, or related field.

• 15+ years in interconnect/system architecture, SI/PI, and highspeed link design for largescale systems (servers, accelerators, networking, or comparable).

• Proven silicon-package-board codesign experience: channel definition, PHY requirements,equalization/FFE/DFE tradeoffs,retimer/redriverchoices, and endtoend closure.

• Handson modeling & simulation (e.g., IBISAMI/Statistical/TimeDomain, Sparameter manipulation, eye/jitter analysis) and relevant EDA/EM tools (e.g., HFSS, Clarity/Siemens/Ansys, ADS,Sigrity, HSPICE/PrimeSim, MATLAB/Python).

• Demonstrated crossfunctional leadership and communication skills-able to drive architecture decisions and tradeoffs with senior technical leaders.

• Proven analytical and problem-solving skills with a focus on performance optimization.

• Proven intellectual curiosity and a passion for challenging the status quo and driving disruptive innovation

• PhD in EE/CE/Physics(or equivalent).

• Expertisewith PCIe Gen6/Gen7 (PAM4), Ethernet112G/224GPAM4, UCIe/XSR/USR links,retimer/redriver,CPC and CPOconsiderations.

• Experience with advanced packaging (2.5D/3D, HBM, organic/ABF, glass/interposers), substrate design rules, and warpage/thermomechanical interactions.

• Systemlevel architecture across node/rack/cluster, including thermalmechanical constraints, serviceability, and manufacturability at cloud scale.

• Track recordof public technical contributions (e.g., DesignCon/Hot Interconnects/OFCS papers, standards proposals), patents, or opensource/consortia leadership.

• Deep insight in global supply chain dynamics and technologytrends