Senior Principal Memory Architect

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

• Architect high-performance HBM/DDR memory subsystemsfor Marvell's custom compute products, including developing specifications, performance models, and product requirements.
• Define and evolve Marvell's memory controller architecture strategy and roadmap, partnering with customers and internal teams to deliver optimal solutions for next-generation workloads.
• Drive micro-architecture development, design specifications, and verification plans in close collaboration with RTL, physical design, and validation teams.
• Develop system-level modelsto evaluate and optimize performance (throughput, latency, QoS, power, area) across multiple design options.
• Collaborate cross-functionally with hardware, firmware, and validation organizations to ensure end-to-end product quality, performance, and reliability.
• Lead innovation initiativesaround memory subsystem architecture, including ECC, RAS, and reliability improvements for server-class products.
• Represent Marvell in technical discussions with customers and ecosystem partners, influencing industry direction and technical decisions.

On-site requirement:This role is 100% in-office at our Santa Clara, Irvine or Boise locations five days per week (no remote or hybrid work option).

What We're Looking For

• Education:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field and 15+ yearsof relevant experience, or
  • Master's/PhD with 8+ yearsof experience in memory architecture or system design.
• Technical Expertise:
  • Deep understanding of DDR/HBM memory subsystem architecturefor data center compute, AI, or XPU systems.
  • Proven experience designing or specifying HBM/DDR memory controllersand associated subsystems.
  • Strong familiarity with JEDEC standards(HBM3/4, DDR4/5, LPDDR5/5X/6) and related memory interface technologies.
  • Experience with system modeling and performance analysistools for evaluating memory system trade-offs.
  • Demonstrated experience developing ECC, RAS, and reliability featuresfor server or high-performance SoC designs.
• Soft Skills:
  • Strong analytical and conceptual thinking with a track record of innovation.
  • Excellent communication skills and the ability to collaborate effectively across global, multi-disciplinary teams.
  • Passion for architecting memory solutions that redefine performance and efficiencyin data center computing

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.